1. Field of the Invention
The present invention relates to a CPU (Central Processing Unit) core suitable for use in a single-chip microcomputer and which is operable at high speed and small in chip size.
2. Description of the Prior Art
In the field of the art to which the present invention pertains, elaborate technologies have been reported by Yamads et al in "8-Bit Flexible Microcontroller", the Institute of Electronics and Communication Engineers of Japan, Materials for Study Meeting, SSD86-92, pp. 7-12, 1986 (hereinafter referred to as document 1), and also reported in "Opening of CPU Core ASIC Age", Nikkei Microdevices, No. 1989-1, pp. 35-43, BP Company (hereinafter referred to as document 2).
There is an increasing demand for a single-chip microcomputer which allows peripheral circuits matching particular applications to be built therein without consuming a long time for development. To meet such a demand, the document 1 proposes a core device in the form of a CPU core to which desired peripheral circuits may be interconnected according to the user's needs. This kind of single-chip microcomputer or so-called ASIC microcomputer chip will have optimum specifications matching a desired application.
A CPU core intended for the above purpose has to adapt itself to various kinds of applications. Hence, prerequisites with such a CPU core are, among others, rapid operation processing, extended design freedom, ease of connection of peripheral circuits, small exclusive area, a broad operable range (voltage, temperature and so forth). The document 1 teaches a CPU core made up of various blocks such as a CPU block, an interrupt control block, an input/output control block, and a RAM, and configured to execute instruction processing by sixteen bits for the purpose of promoting high-speed operations.
However, a CPU core having the above configuration has some problems left unsolved. Namely, increasing the processing speed and reducing the exclusive area for a CPU core are contradictory to each other. Fetching an instruction from a ROM, executing pipeline processing, and providing the processing system with a 16-bit width as disclosed in the document 1 are typical approaches available for enhancing high-speed operations. However, all of such approaches would complicate the hardware of an 8-bit microcomputer and would increase the exclusive area for the CPU core due to the increase in processing speed.
The prior art CPU core includes RAMs, clock generators, and various control circuits therein and is satisfactory so long as a desired application can be implemented by the specifications of such built-in components. However, when the specifications cannot meet the user's demand, e.g. , when the number of RAMS should be increased or decreased or when the specifications of the control circuits should be changed, it is necessary to redesign the portions of the CPU core where the specifications should be changed and to adequately distribute the functions to the CPU core and the peripheral circuits to be connected to the CPU core. This kind of CPU core, therefore, is not fully satisfactory when it comes to the ease of connection of peripheral circuits and the design freedom available for the peripheral circuits.
Hence, the configuration of a CPU core has decisive influence on the design freedome of peripheral circuits and the chip size. When a CPU core has a great number of components, the user-oriented selectable range of specifications is extremely limited and the chip size is increased. The resultant CPU core would be contrary to the intention, i.e. , a broad range of applications. If the number of components of a CPU is relatively small, the design freedom of peripheral circuits will be enhanced and the chip-size will be reduced. Such a CPU, however, would increase the user's burden concerning the design of peripheral circuits and would require manifold know-hows on CPUs for the connection of peripheral circuits to the CPU core. This impedes the reduction of developing time which is the object of an ASIC microcomputer. Thus, a CPU core for an ASIC microcomputer which allows various kinds of peripheral circuits to be efficiently and easily connected thereto, i.e. , which has ample design freedom has not been reported yet.